Power-aware Speed-up for Multithreaded Numerical Linear Algebraic Solvers on Chip Multicore Processors

Jayanta Mukherjee, Soumyendu Raha

Abstract


With the advent of multicore chips new parallel computing metrics and models have
become essential for re-designing traditional scientific application libraries tuned to a single
chip. In this paper we evolve metrics specific to
generalized chip multicore processors (CMP) and use them for parallel performance modeling of
numerical linear algebra
routines that are commonly available as shared object libraries tuned to single processor chip.
The study uses a thread parallel model of parallel computing on CMPs.
POSIX threads (pthread) have
been used due to the wide acceptance and availability.
The shortcoming of the POSIX threads for numerical
linear algebra in terms of data distribution has been overcome by tuning algorithms
so that a particular thread will operate on a specific portion of the
matrix. The paper studies tuned implementations of the conventional a few parallel
linear algebra method as examples on a generalized CMP model.
For formulating a speed-up metric, this work takes into consideration the
power consumption and the effect of memory cache hierarchy.

References



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