The present and the future of reconfigurable devices for space applications

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Beatriz Aparicio del Moral
Julio Rodríguez-Gómez
Antonio C. López Jiménez

Abstract

Introduction

Space missions present important scientific and technological challenges. Electronic systems used in space applications require low power consumption, small weight and small size. Designers should take into account that each gram sent to space requires a very large amount of money. Furthermore, the electronics must be highly reliable in order to work for years in hostile environments [1]. One of the main inconveniences with instruments designed for space is that they must be resistant to radiation. This requirement depends mostly on the type of mission and its duration.

FPGAs began space missions by acting as glue logic. Only one chip could do the work of several more (controllers, clock divisors, decoders…). Currently, FPGAs technologies are more and more versatile and reconfigurable devices can be used as complex controllers, or as the main control system, combining several system functions on a single chip, including microprocessors functionality and small size memory. Because of the special environmental conditions in these kinds of missions, the designers are forced to utilize suitable devices adapted to support radiation and extreme temperatures. As a consequence, it is not possible to use the latest technologies in a space mission, because the use of these technologies in a space environment use is complex. In spite of this, the number of space missions has been increasing, and electronics manufacturers now have sections that are dedicated to the aerospace market. This is one of the reasons that has motivated the rapid evolution in the use of FPGAs devices.

In this editorial we present the current state of reconfigurable hardware and the feasible future evolution of this technology in this field. We review the configurable devices that are suitable for flight. We give some examples of missions where FPGAs have been used successfully and finally, we draw some conclusions about the use of these devices.

Review of FPGAs for space applications

As commented before, the devices onboard a spacecraft must be light, small size, with very low power consumption, radiation resistant, and as a main requirement, they must guarantee very high reliability. The choice of a suitable device depends mostly on the kind of mission, the environment and on the life span. The requirements for a satellite that will be working in space for one year are radically different from requirements for a spacecraft going to Mars and working for six years [2].

The farther we go, the more difficult it is to find suitable devices. This motivates the choice of devices that are known to be reliable and have a good track record over multiple missions. An example is the Intel 8086 processor, which is still used for space missions like the Mars Pathfinder and GIADA in Rosetta [3]. The same reasoning can be applied to FPGA devices. The ones that we can use are unfortunately not those that represent the latest technology advances. Nevertheless, FPGAs that are suitable for space have evolved and today designers can find products with a million usable equivalent gates that are suitable for flight.

Space agencies (NASA and ESA) offer public parts lists with preferred devices to go onboard a space mission [4, 5]. But these lists are not completely exhaustive, because they do not have all the space devices. In the lists, we can see European devices are nonvolatile, whereas NASA preferred devices are reprogrammable Few reprogrammable devices have been used on European spacecrafts due to their sensitivity to single event upsets (SEUs). But recently, FPGA vendors have begun to develop SEU mitigation techniques to make their devices usable in space applications [6].

There are two main FPGA manufacturers: Actel and Xilinx, although there are more vendors offering FPGAs for flight: Aeroflex and Atmel. In this editorial we focus on Actel and Xilinx. Actel offers non reprogrammable FPGAs for space applications, with the SX and Axcelerator families. They are antifuse-based devices [7], non reprogrammable, but radiation tolerant, with total ionization dose (TID) up to 300K rads. The main features are 250MHz system performance and from 48k up to 108k system gates for the SX family, and 350MHz system performance and 250k to 4 million system gates for the Axcelerator family. The advantages of these devices are the availability of prototyping using non-qualified devices, and Single Even upset (SEU) mitigation techniques such as triple modular redundancy (TMR) implemented automatically on the chip. These devices also feature error detection and correction (EDAC) for internal memory, and they are power on and go, that is, they do not need other components to start working, because the program is already on the device when the system is powered on. In reprogrammable devices, it is necessary to add some other chip containing the program, so when the system is powered on, the program has to be written onto the FPGA.

Xilinx offers reprogrammable devices based on the QPro-R Virtex and QPro-R Virtex II devices [8]. They are claimed to be powerful and flexible alternatives to mask-programmed gate arrays. The main features are reprogrammability, 200 MHz system performance and system gates from 300K to 1M gates for Virtex and 300 MHz system performance and 1M to 6M gates for Virtex II devices. The TID is 100KRads for the first family and 200KRads for the second one. The advantage of these devices is the reprogramability itself and, because there are no significant differences compared to the commercial versions, the standard devices could be used for reducing system prototyping cost.

Some FPGA vendors (i.e. Atmel and Xilinx) provide the possibility of migrating FPGA designs to ASICs. This can be used, for example, in a constellation of satellites.

Traditionally only antifuse devices (such as the one provided by Actel) have been used for the space missions. The applicability of reprogrammable devices (such as the one offered by Xilinx) has started to be in use in the last years [9].

If we compare these two types of FPGAs (antifuse and reprogrammable devices), there are also other features that should be taken into account. On the one hand, antifuse families offer TRM implementation in an automatic way, and SEU protection for internal registers, whilst reprogrammable devices do not [7, 8]. On the other hand, reprogrammable devices offer a high integration density. In addition, they provide advanced interfacing solutions with a broad range of electrical standards, clock management features and internal memory capacity [10]. Nevertheless, this family requires an external device to load the bitstream at power on. This means more components and an additional risk during a very critical moment like the start up of the system. As a consequence, the choice between these two alternative devices depends on the application, and should be taken after a careful analysis of the mission requirements.

FPGAs used in space missions

In this section we will review some space missions that have successfully used FPGAs, and are already on space.

The Institute de Astrophysics of Andalucía has been involved in several space missions; the most extended experience is with OSIRIS and GIADA instruments, and we will refer these.

There are many differences between designing for space and designing for another application. Space designers must take into account the final implementation of their designs, that is, the logic generated from their code. This can be different from working in other area, where only the final result is significant. In space, the logic is important because of the necessity of preventing SEU and other radiation effects, making the instrument as safe as possible [11]. The OSIRIS instrument of the Rosetta mission is an optical spectroscopic and Infrared remote imaging system. It has several parts, and FPGAs have been used to improve the design. In the CCD readout box, there are two FPGAs, one for the clocks, and the other to handle high speed serial [12]. The mechanism controller board (MCB) of the two OSIRIS optical cameras also has two FPGAs to implement the digital control circuits [13]. Data gathering, packaging, transmission and command decoding are performed within the FPGAs (Actel RH1280). In this case, FPGAs have made significant advances, allowing the reduction of mass and making the design simpler. In fact. the motor controller FPGA makes an a dco controller optimized for this instrument with different and very specific functionalities.

The GIADA instrument, also of the Rosetta mission is a grain impact analyzer and dust accumulator experiment. It uses one FPGA to control the data obtained from the proximity electronics [3, 2]. This makes possible the use of an Intel 8086 processor, because there are tasks done by the FPGA, leaving the processor free to do other operations. All the FPGAs used in GIADA are Actel, RH1280. The use of Actel RH1280 allows significant reduction of power consumption and also makes the design simpler, because one chip implements the same function as a microcontroller with all the peripheries and EDAC techniques for mitigating SEU. The mass and size are obviously small in this solution.

Spirit and Discovery missions utilize XQVR1000 and XQR4062XLs from Xilinx. The XQR4062XLs were used during the descent and landing of the rovers on the surface of Mars, while XQVR1000s were used to control all of the brushed DC and stepper motors for the wheels, steering, antennas, camera, and other instruments on the rovers themselves [9].

Almost all future space missions that are presently being developed are going to use FPGAs onboard. An example of those in which the IAA is working is, for example, MEDUSA, the acronym for martian environmental dust systematic analyzer. It will analyze the dust on the surface of Mars, onboard the EXOMARS mission [14]. The main electronics will include an FPGA from Actel, with a programmable finite state machine inside, the clock generation control, and all the controllers for communication, digital acquisition, data handling, and an embedded overall controller.

Other future projects include: (1) the SOPHI experiment which willl be onboard the solar orbiter mission. It is a polarimetric helyospheric image magnetograph for studying the sun. (2) the SODA experiment which will be onboard the Solar Orbiter mission also. It is an instrument devoted to study cosmic dust. (3) BELA is a Laser Altimeter going onboard the Bepi-Colombo mission. In all these missions FPGAs will play a relevant role making the system electronics simple and of high reliability at the same time.

Conclusions

Design for space environment is complicated due to the very high requirements. Factors such as weight, power and size must be taken into account. Among all of these, the most important requirement is reliability and one of the most important problems is the effect of radiation. For these reasons it is necessary to use devices especially built for space environments. The manufactures have specific areas for the aerospace market and this has motivated space agencies to have preferred parts lists to help designers to choose the devices to use onboard.

In the past, devices were more primitive. Therefore, FPGAs were used as glue logic. To use them, designers utilized schematic as a popular design technique. Nowadays, configurable devices can be employed as many complex systems on just one chip. We can find devices with a million gates on the market, and it is not the practice to use schematic, because of the complexity. For these reasons, designers are turning to hdl languages, which offer less control of the logic used, but yield a design simpler than a scheme.

There are two main types of configurable devices. One time programmable devices (OTP) like that offered by Actel, and reprogrammable devices like that offered for Xilinx. Both have advantages and disadvantages, and care should be taken before choosing one device.

Companies like Actel now have new FPGA devices, based on flash technology. These devices have all the advantages from reprogramability, and from Power and Go. They are still not qualified for space, but in the future it is reasonable to believe they will be. In addition, new technological advances such as dynamic reconfiguration can represent an important step in the future of space missions. This would offer the possibility of making substantial changes in hardware on the fly, giving options to add new functionalities or function modes, and replacing software patches.

One important feature that we believe will be of relevant importance for the future of FPGA devices in space mission is their capability of developing programmable system-on-chip (PSoC) in just one single device. Nowadays there are FPGA synthesizable versions of processors such as the Leon processor [15], which has been qualified for space applications [16]. Codesign techniques could be applied to split the different tasks in such a way that algorithm and scheduling tasks are implemented in the processor while low level controlling tasks are developed using the device logic gates. Moreover, traditional glue logic tasks could still be done on the same chip. For demanding extensive computations, the FPGA logic could be used to developing a custom coprocessor to help the processor in these computations, making possible full parallel processing. This feature is not achievable using a single microprocessor., But using programmable hardware, we can do several tasks simultaneously.

FPGAs play a relevant role in space missions, and it is reasonable to believe that in the future the use of these devices will be even more extensive. Their capabilities to act as glue logic and as overall controllers, all in a single chip, make them the perfect devices to go onboard space craft. We believe FPGA devices will be the predominant digital device for space missions in the near future.

 

References
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Beatriz Aparicio del Moral,
Julio Rodríguez-Gómez,
Antonio C. López Jiménez.

Institute of Astrophysics of Andalucía,
Intrumental and Technological Development Unit,
Higher Council of Scientific Research (CSIC).


{bea, julio, antonio}@iaa.es

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Section
Editorial