On the Potential of NoC Virtualization for Multicore Chips

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J. Flich
S. Rodrigo
J. Duato
T. Sodring
Ã. G. Solheim
T. Skeie
O. Lysne


As the end of Moores-law is on the horizon, power becomes a limiting
factor to continuous increases in performance gains for single-core
processors. Processor engineers have shifted to the multicore paradigm
and many-core processors are a reality. Within the context of these
multicore chips, three key metrics point themselves out as being of
major importance, performance, fault-tolerance (including
yield), and power consumption. A solution that optimizes all
three of these metrics is challenging. As the number of cores increases
the importance of the interconnection network-on-chip (NoC) grows as
well, and chip designers should aim to optimize these three key
metrics in the NoC context as well.

In this paper we identify and discuss the main properties that a NoC
must exhibit in order to enable such optimizations. In particular, we
propose the use of virtualization techniques at the NoC level. As a major finding, we identify the
implementation of unicast and broadcast routing algorithms to become a key design parameter
in order to achieve an effective virtualization of the chip.

The intention behind this paper is for it to serve as a position paper
on the topic of virtualization for NoC and the challenges that should
be met at the routing layer in order to optimize performance,
fault-tolerance and power consumption in multicore chips.

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